JFET Amplifier

Figure 1. JFET Amplifier.

The first point in the design is to determine the working point. Then we need data on the transistor, as for example shown in the next figure for the transistor 2SK170. This is no longer produced, but LSK170 is the name of the replacement that is now being produced.

Figure 2. JFET characteristics.

In the characteristic on the left is added the load line for the resistor R_S = 36 ohm. When the drain current is 0, V_GS = 0 V since gate (G) is at 0 V (it is assumed that the gate current is equal to 0). When V_GS = −0.3 V, the drain current I_D = 8.3 mA. Then we can draw the red line as shown in the figure. The transistor is sorted out by saturation current (I_DSS). If we choose I_DSS  = 10 mA, we will see that the drain current with our source resistor R_S is just below I_D = 5 mA. Then our V_GS ≈−0.17 V. Note that our maximum signal amplitude between gate and source is equal to this value. In practice, it is not a good idea to apply such a large signal voltage since we will then have a very high distortion. With I_D = 5 mA, the voltage drop across the drain resistor R_D will be equal to V_RD = 5∙2.4 = 12 V. Then the voltage on the drain will be V_D = 24-12 = 12 V, since our V_DD = 24 V.

In order to calculate the voltage gain, we must know the transconductance. This tells us how sensitive the small signal drain current i_d is to changes in the control voltage, the gate-source voltage v_gs:

The transconductance is found on the right in figure 2. There we read g_m = 30 mA/V (mS) for I_D = 5 mA. To find the voltage gain, we can use a standard small signal model for JFET. The simplest possible small signal model is shown in figure 3a.

Figure 3. JFET small signal models.

Here we will first use the simple model in figure 3a. Then we can draw the amplifier shown in figure 1 with this model. We have assumed that V_DD has a very low internal impedance so that R_D can be shorted to 0 V. We have also assumed that C_D is shorting small signals. This means that R_D og R_L are in parallel on the drain, see the figure below.

Figure 4. Amplifier with JFET model.

From the figure we can see that the input voltage for i_d = g_mv_gs is given by:

On the drain the load R_L is in paralell with R_D, R_d = R_D||R_L. Then the output voltage v_out is:

The voltage gain from gate to drain is the realationship between the voltage at the output and the voltage at the input:

The denominator states what is known as the feedback factor. This corresponds to the factor with which the voltage gain is reduced by the so-called source degeneration due to R_S. The feedback factor is then:

If we assume that the amplifier is unloaded, that is, we remove R_L, the voltage gain is:

Simulations can be a useful tool for analyzing electronics design. However, there should be models for the individual components. The components that are most difficult to model for discrete designs are semiconductors. If models do not exist, detailed data sheets must be available for such models to be generated. For our JFET, there is a model in SPICE that can be used. However, it has an I_DSS = 12.3 mA for V_DS = 12 V, so that the drain current is slightly higher than 5 mA found above.

The output resistance is the resistance seen from the load. In the audio area, we can assume that C_D is shorting. From figure 4 we can see that the output resistance is equal to R_D, in other words equal to 2.4 kΩ. In reality, it will be somewhat lower, this is because the drain current rises slightly with the drain-source voltage. This so-called Early effect is modeled with r₀ in figure 3b. The output characteristic shown below can be used to determine this.

Figure 5. Input and output characteristics for JFET SK170.

A not too accurate reading gives us r₀ = 10 V/0.5 mA = 20 kΩ. But r₀ is not directly in parallel with R_D, but is increased approximately by the feedback factor B (from equation 5). The output resistance is then approximately:

It is a fairly common practice to select the cut-off frequency below 2 Hz. If we say that the minimum load resistance is 10 times R_D, i.e. R_L = 24 kohm, we can find a minimum capacitor size by solving with respect to C_D in the equation above:

A calculation of the upper cut-off frequency is only possible as long as the source impedance is known. We will therefore only show an example with a source resistance of 1 kΩ. We must then use the equivalent in figure 3c. Excerpts from data sheets for the transistor SK170 are shown below.

Figure 6. JFET capacitances.

Figure 7. High frequency equivalent for the JFET amplifier.

The capacitor C_g0 is C_iss reduced by the feedback factor B (from equation 5). The capacitor C_d0, the so-called Miller capacitor, is the capacitor C_rss multiplied by the gain A_v from gate to source (from equation 6). The upper cut-off frequency will be the inverse of the time constant T_g on the gate:

Here we have omitted R_G i n the calculation since  R_p (in series with gate) is much smaller than this resistance. The upper cut-off frequency will then be:

A simulation gives an upper cut-off frequency of 690 kHz. Not least considering the variation in C_rss, we see that our calculation method gives a pretty good result compared to the simulator.

In an MM Phono amplifier, for example, it is important to use low noise transistors and to be able to calculate the signal-to-noise ratio of the amplifier. Our JFET is a low-noise type, as can be seen from the noise voltage density of this transistor shown in the figure below.

Figure 8. Noise voltage density for JFET SK170.

The noise voltage density is referred to gate. It is therefore common to refer all noise voltages to gate. Since uncorrelated noise powers are summed, consequently noise voltages must be added squarely. The figure below shows the amplifier with the individual noise voltage contributions.

Figure 9. JFET amplifier with noise equivalent.

The amplifier is thought to be connected to a generator with a generator resistor (R_p in figure 7). This consequently is in parallel with R_G (the signal voltage is short-circuited for noise calculation). Consequently, the noise voltage from these resistors is given by:

Here k is equal to Boltzman's constant, 1.38·10^-23 J/K, T is the temperature in Kelvin (0 K = −273.15 °C) and B is the noise bandwidth in Hertz. The noise voltage v_NO represents the noise from the output (drain resistor) transformed to the input:

V_N represents the noise voltage from the transistor, given by the noise voltage density in Figure 8. This is then:

From figure 8, E_n ≈ 0.85 nV/√Hz can be read for a drain current of 5 mA. Total noise at the input is consequently:

With inserted expressions:

If we assume a source resistance of R_p = 1 kΩ, a noise bandwidth B = 20 kHz and a temperature of T = 298 K, this gives the noise voltage:

A low-noise amplifier is also characterized by the signal-to-noise ratio. If a signal of, for example 6 mV (RMS value), is applied to the amplifier, the signal-to-noise ratio is given by: