# JFET Amplifier

As an example on the design of a JFET voltage amplifier we can use the input stage for my MM Phono amplifier as an example. The schematic is shown below. There is no blocking capacitor on the gate (G), but it is a necessity on the drain (D). The load on the amplifier is RL. Figure 1. JFET Amplifier.

The first point in the design is to determine the working point. Then we need data on the transistor, as for example shown in the next figure for the transistor 2SK170. This is no longer produced, but LSK170 is the name of the replacement that is now being produced. Figure 2. JFET characteristics.

In the characteristic on the left is added the load line for the resistor RS = 36 ohm. When the drain current is 0, VGS = 0 V since gate (G) is at 0 V (it is assumed that the gate current is equal to 0). When VGS = −0.3 V, the drain current ID = 8.3 mA. Then we can draw the red line as shown in the figure. The transistor is sorted out by saturation current (IDSS). If we choose IDSS  = 10 mA, we will see that the drain current with our source resistor RS is just below ID = 5 mA. Then our VGS −0.17 V. Note that our maximum signal amplitude between gate and source is equal to this value. In practice, it is not a good idea to apply such a large signal voltage since we will then have a very high distortion. With ID = 5 mA, the voltage drop across the drain resistor RD will be equal to VRD = 52.4 = 12 V. Then the voltage on the drain will be VD = 24-12 = 12 V, since our VDD = 24 V.

In order to calculate the voltage gain, we must know the transconductance. This tells us how sensitive the small signal drain current id is to changes in the control voltage, the gate-source voltage vgs: The transconductance is found on the right in figure 2. There we read gm = 30 mA/V (mS) for ID = 5 mA. To find the voltage gain, we can use a standard small signal model for JFET. The simplest possible small signal model is shown in figure 3a. Figure 3. JFET small signal models.

Since the drain current increases slightly with the drain-source voltage, the model shown in Figure 3b is more accurate. And if the capacitances between gate and source as well as between gate and drain are introduced, a model for high frequencies is obtained as shown in figure 3c.

Here we will first use the simple model in figure 3a. Then we can draw the amplifier shown in figure 1 with this model. We have assumed that VDD has a very low internal impedance so that RD can be shorted to 0 V. We have also assumed that CD is shorting small signals. This means that RD og RL are in parallel on the drain, see the figure below. Figure 4. Amplifier with JFET model.

From the figure we can see that the input voltage for id = gmvgs is given by: On the drain the load RL is in paralell with RD, Rd = RD||RL. Then the output voltage vout is: The voltage gain from gate to drain is the realationship between the voltage at the output and the voltage at the input: The denominator states what is known as the feedback factor. This corresponds to the factor with which the voltage gain is reduced by the so-called source degeneration due to RS. The feedback factor is then: If we assume that the amplifier is unloaded, that is, we remove RL, the voltage gain is: Please observe that  RL should be much larger than RD. If RL = RD, the gain is halved.

Simulations can be a useful tool for analyzing electronics design. However, there should be models for the individual components. The components that are most difficult to model for discrete designs are semiconductors. If models do not exist, detailed data sheets must be available for such models to be generated. For our JFET, there is a model in SPICE that can be used. However, it has an IDSS = 12.3 mA for VDS = 12 V, so that the drain current is slightly higher than 5 mA found above.

With this model we find that ID = 5.3 mA so that the DC voltage on the collector is equal to 11.5 V. The gain is equal to 34.7 times, i.e. the same we found with our simple model above.

We have used RG to determine the input resistance Rin to the amplifier. It will then be equal to Rin = 47 kΩ. Assuming that the gate current is approximately equal to 0 does not lead to an excessive error.

The output resistance is the resistance seen from the load. In the audio area, we can assume that CD is shorting. From figure 4 we can see that the output resistance is equal to RD, in other words equal to 2.4 kΩ. In reality, it will be somewhat lower, this is because the drain current rises slightly with the drain-source voltage. This so-called Early effect is modeled with r0 in figure 3b. The output characteristic shown below can be used to determine this. Figure 5. Input and output characteristics for JFET SK170.

A not too accurate reading gives us r0 = 10 V/0.5 mA = 20 kΩ. But r0 is not directly in parallel with RD, but is increased approximately by the feedback factor B (from equation 5). The output resistance is then approximately: A simulation gives a slightly higher output resistance, so assuming that the output resistance is approximately equal to RD, is not that wrong. But again, it depends on how good the model in the simulator is.
A relatively simple calculation is finding the lower cut-off frequency for the gain. Since we only have one capacitor to consider, the cut-off frequency fn is given as the inverse of the time constant T at the output: It is a fairly common practice to select the cut-off frequency below 2 Hz. If we say that the minimum load resistance is 10 times RD, i.e. RL = 24 kohm, we can find a minimum capacitor size by solving with respect to CD in the equation above: A natural choice would then be to choose CD = 3.3 uF. A simulation with RL = 24 kΩ then gives a cut-off frequency equal to 1.8 Hz and a gain in the audible range equal to 30.0 dB.

A calculation of the upper cut-off frequency is only possible as long as the source impedance is known. We will therefore only show an example with a source resistance of 1 kΩ. We must then use the equivalent in figure 3c. Excerpts from data sheets for the transistor SK170 are shown below. Figure 6. JFET capacitances.

In the data sheet for the transistor we find that Ciss = 30 pF and Crss = 6 pF. These are approximate values, and the latter increases with reduced gate-drain voltage. To simplify the calculations, we can draw an equivalent as shown below. Figure 7. High frequency equivalent for the JFET amplifier.

The capacitor Cg0 is Ciss reduced by the feedback factor B (from equation 5). The capacitor Cd0, the so-called Miller capacitor, is the capacitor Crss multiplied by the gain Av from gate to source (from equation 6). The upper cut-off frequency will be the inverse of the time constant Tg on the gate: Here we have omitted RG i n the calculation since  Rp (in series with gate) is much smaller than this resistance. The upper cut-off frequency will then be: A simulation gives an upper cut-off frequency of 690 kHz. Not least considering the variation in Crss, we see that our calculation method gives a pretty good result compared to the simulator.

In an MM Phono amplifier, for example, it is important to use low noise transistors and to be able to calculate the signal-to-noise ratio of the amplifier. Our JFET is a low-noise type, as can be seen from the noise voltage density of this transistor shown in the figure below. Figure 8. Noise voltage density for JFET SK170.

The noise voltage density is referred to gate. It is therefore common to refer all noise voltages to gate. Since uncorrelated noise powers are summed, consequently noise voltages must be added squarely. The figure below shows the amplifier with the individual noise voltage contributions. Figure 9. JFET amplifier with noise equivalent.

The amplifier is thought to be connected to a generator with a generator resistor (Rp in figure 7). This consequently is in parallel with RG (the signal voltage is short-circuited for noise calculation). Consequently, the noise voltage from these resistors is given by: Here k is equal to Boltzman's constant, 1.38·10-23 J/K, T is the temperature in Kelvin (0 K = −273.15 °C) and B is the noise bandwidth in Hertz. The noise voltage vNO represents the noise from the output (drain resistor) transformed to the input: Here Av is given as the voltage amplification from gate to drain, as calculated earlier. The gain from gate to source is approximately equal to 1. Thus, the noise voltage from the source resistance on gate is given by: VN represents the noise voltage from the transistor, given by the noise voltage density in Figure 8. This is then: From figure 8, En 0.85 nV/Hz can be read for a drain current of 5 mA. Total noise at the input is consequently: With inserted expressions: If we assume a source resistance of Rp = 1 kΩ, a noise bandwidth B = 20 kHz and a temperature of T = 298 K, this gives the noise voltage: Due to the high gain, the collector resistance's contribution to the noise is negligible. It is equivalent to a resistor of 2 Ω on gate. And since the source resistor is also much larger than the source resistor, we are left with the conclusion that it is the source resistor that has the largest noise contribution, about 4nV/√Hz, compared to the transistor's 0.85 nV / √Hz.Also note that if we do not connect the amplifier to a source (the input is open), the noise voltage will increase by a factor of more than 200 times. It should also be noted that the noise bandwidth is assumed to be 20 kHz. This is too low if we do not limit the frequency band of the amplifier. A simulation also confirms the value of the noise voltage found above.

A low-noise amplifier is also characterized by the signal-to-noise ratio. If a signal of, for example 6 mV (RMS value), is applied to the amplifier, the signal-to-noise ratio is given by: This is a respectable value with the reservations mentioned.

Amplifier distortion can be found by allowing ID to be a function of gain. It provides a transconductance that is not only gm reduced due to feedback. The drain current will not only depend on vin, but also on vin2, vin3 and so on. This results in harmonics of 2nd, 3rd, 4th etc, which gives us the total harmonic distortion.

The procedure is time consuming, so we leave it here. Instead, we must use the simulator. With an input signal of 50 mV, a source resistance of 1 kΩ and a load of 24 kΩ, a total harmonic distortion of 0.68% is the result. The distortion is completely dominated by the 2nd harmonic while the 3rd harmonic is over 30 times lower. There are also very small values for 4th and 5th harmonics. With an input signal of 25 mV, the distortion is halved.