Figure
1. JFET Amplifier. 
The first point in the design is to determine the working point. Then we need data on the transistor, as for example shown in the next figure for the transistor 2SK170. This is no longer produced, but LSK170 is the name of the replacement that is now being produced.
Figure 2. JFET characteristics. 
In the characteristic on the left is added the load line for the resistor R_{S} = 36 ohm. When the drain current is 0, V_{GS} = 0 V since gate (G) is at 0 V (it is assumed that the gate current is equal to 0). When V_{GS} = −0.3 V, the drain current I_{D} = 8.3 mA. Then we can draw the red line as shown in the figure. The transistor is sorted out by saturation current (I_{DSS}). If we choose I_{DSS} = 10 mA, we will see that the drain current with our source resistor R_{S} is just below I_{D} = 5 mA. Then our V_{GS} ≈−0.17 V. Note that our maximum signal amplitude between gate and source is equal to this value. In practice, it is not a good idea to apply such a large signal voltage since we will then have a very high distortion. With I_{D} = 5 mA, the voltage drop across the drain resistor R_{D} will be equal to V_{RD} = 5∙2.4 = 12 V. Then the voltage on the drain will be V_{D} = 2412 = 12 V, since our V_{DD} = 24 V.
In order to calculate the voltage gain, we must know the transconductance. This tells us how sensitive the small signal drain current i_{d} is to changes in the control voltage, the gatesource voltage v_{gs}:
The transconductance is found on the
right in figure 2. There we read g_{m} = 30 mA/V (mS) for I_{D}
= 5 mA.
To find the voltage gain, we can use a standard small
signal model for JFET. The simplest possible small signal model is shown in
figure 3a.
Figure 3. JFET small signal models. 
Here we will first use the simple model in figure 3a. Then we can draw
the amplifier shown in figure 1 with this model. We have assumed that V_{DD}
has a very low internal impedance so that R_{D} can be shorted
to 0 V. We have also assumed that C_{D} is shorting small
signals. This means that R_{D}
og R_{L} are in parallel on the drain, see the figure below.
Figure 4. Amplifier with JFET model. 
From the figure we can see that the input voltage for i_{d} = g_{m}v_{gs} is given by:
On the drain the load R_{L} is in paralell
with R_{D},
R_{d}
= R_{D}R_{L}. Then the output voltage v_{out}
is:
The voltage gain from gate to drain is the realationship between the voltage at the output and the voltage at the input:
The denominator states what is known as the feedback factor. This corresponds to the factor with which the voltage gain is reduced by the socalled source degeneration due to R_{S}. The feedback factor is then:
If we assume that the amplifier is unloaded, that is, we remove R_{L}, the voltage gain is:
Simulations can be a useful tool for
analyzing electronics design. However, there should be models for the
individual components. The components that are most difficult to model
for discrete designs are semiconductors. If models do not exist,
detailed data sheets must be available for such models to be generated.
For our JFET, there is a model in SPICE that can be used. However, it
has an I_{DSS} = 12.3 mA for
V_{DS} = 12 V, so that the drain current is slightly higher
than 5 mA found above.
The output resistance is the
resistance seen from the load. In the audio area, we can assume that C_{D}
is shorting. From figure 4 we can see that the output resistance is
equal to R_{D}, in other words equal to 2.4 kΩ. In reality, it
will be somewhat lower, this is because the drain current rises
slightly with the drainsource voltage. This socalled Early effect is
modeled with r_{0} in figure 3b. The output characteristic
shown below can be used to determine this.
Figure 5. Input and output characteristics for JFET SK170. 
A not too accurate reading gives us r_{0} = 10 V/0.5 mA = 20 kΩ. But r_{0} is not directly in parallel with R_{D}, but is increased approximately by the feedback factor B (from equation 5). The output resistance is then approximately:
It is a fairly common practice to
select the cutoff frequency below 2 Hz. If we say that the minimum
load resistance is 10 times R_{D}, i.e. R_{L} = 24
kohm, we can find a minimum capacitor size by solving with respect to C_{D}
in the equation above:
A calculation of the upper cutoff frequency is only possible as long
as the source impedance is known. We will therefore only show an
example with a source resistance of 1 kΩ. We must then use the
equivalent in figure 3c. Excerpts from data sheets for the transistor
SK170 are shown below.
Figure 6. JFET capacitances. 
In the data sheet for the transistor we find that C_{is}_{s} = 30 pF and C_{rss} = 6 pF. These are approximate values, and the latter increases with reduced gatedrain voltage. To simplify the calculations, we can draw an equivalent as shown below.
Figure 7. High frequency equivalent for the JFET amplifier. 
The capacitor C_{g0} is C_{is}_{s}
reduced
by the feedback factor B (from equation 5). The capacitor C_{d0}, the socalled Miller
capacitor, is the capacitor C_{rss}
multiplied
by the gain A_{v}
from
gate to source (from equation 6). The upper cutoff frequency will be
the inverse of the time constant T_{g} on the gate:
_{}_{}Here we have omitted R_{G} i n the calculation since R_{p} (in series with gate) is much smaller than this resistance. The upper cutoff frequency will then be:
A
simulation gives an upper cutoff frequency of 690 kHz. Not least
considering the variation in C_{rss},
we see that our
calculation method gives a pretty good result compared to the simulator.
In an MM Phono amplifier, for example, it is important to use low noise
transistors and to be able to calculate the signaltonoise ratio of
the amplifier. Our JFET is a lownoise type, as can be seen from the
noise voltage density of this transistor shown in the figure below.
Figure 8. Noise voltage density for JFET SK170. 
The noise voltage density is referred to gate. It is
therefore common to refer all noise voltages to gate. Since
uncorrelated noise powers are summed, consequently noise voltages must
be added squarely. The figure below shows the amplifier with the
individual noise voltage contributions.
Figure 9. JFET amplifier with noise equivalent. 
The amplifier is thought to be connected
to a generator with a generator resistor (R_{p}
in figure 7). This
consequently is in parallel with R_{G}
(the signal voltage is
shortcircuited for noise calculation). Consequently, the noise voltage
from these resistors is given by:
Here
k is equal to Boltzman's constant, 1.38ˇ10^{23}
J/K, T is the temperature in Kelvin (0 K = −273.15 °C) and B
is the noise bandwidth in Hertz. The noise voltage v_{NO}
represents
the noise from the output (drain resistor) transformed to the input:
V_{N} represents the noise voltage from the transistor, given by the noise voltage density in Figure 8. This is then:
From figure 8, E_{n} ≈ 0.85 nV/√Hz can be read for a drain current of 5 mA. Total noise at the input is consequently:
With inserted expressions:
_{}If we assume a source resistance of R_{p} = 1 kΩ, a noise bandwidth B = 20 kHz and a temperature of T = 298 K, this gives the noise voltage:
Due to the high gain, the collector resistance's contribution to the noise is negligible. It is equivalent to a resistor of 2 Ω on gate. And since the source resistor is also much larger than the source resistor, we are left with the conclusion that it is the source resistor that has the largest noise contribution, about 4nV/√Hz, compared to the transistor's 0.85 nV / √Hz.Also note that if we do not connect the amplifier to a source (the input is open), the noise voltage will increase by a factor of more than 200 times. It should also be noted that the noise bandwidth is assumed to be 20 kHz. This is too low if we do not limit the frequency band of the amplifier. A simulation also confirms the value of the noise voltage found above.
A lownoise amplifier is also characterized by the signaltonoise
ratio. If a signal of, for example 6 mV (RMS value), is applied to the
amplifier, the signaltonoise ratio is given by:
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